(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) has replaced local oxidation of silicon (LOCOS) for formation of active area isolations in integrated circuits with feature sizes of 0.25 microns and below. STI is superior to LOCOS for these applications because of smaller area requirements and better planarity.
Referring now to FIG. 1, a cross section of a prior art integrated circuit device is shown. This cross section illustrates some of the potential problems in the prior art. A semiconductor substrate 10 is provided. Two STI structures 14 have been formed in the semiconductor substrate 10. The STI structures 14 have been formed using conventional processes. In the leftmost example, a trench is etched into the semiconductor substrate 10. A trench filling oxide layer 14 is deposited overlying the semiconductor substrate 10 and filling the trench. The trench filling oxide layer 14 is polished down to the top surface of the semiconductor substrate 10 to complete the STI. Note that some overetching 18 and rounding of the corners occurs. These topological features can cause high leakage currents in the MOS devices formed adjacent to the STI.
In the rightmost example, a different process approach is taken. Typically, a silicon nitride layer, not shown, is deposited overlying the semiconductor substrate 10. The trench is etched through the silicon nitride layer and the semiconductor substrate 10. The trench filling oxide layer 14 is deposited overlying the semiconductor substrate 10 and filling the trench. The trench filling oxide layer 14 is polished down to the silicon nitride layer 14. The silicon nitride layer is then removed to complete the STI. In this example, the topology problems of the leftmost example are prevented. However, the STI now has an elevation that can cause other problems in the formation of surface features near the STI.
Referring now to FIG. 2, the use of the STI structures with a MOS transistor is illustrated. The STI structures 34 are typically formed first into the semiconductor substrate 30. The MOS gate structure, comprising a gate oxide 38 and a polysilicon gate electrode 42, is then formed overlying the semiconductor substrate 30. The lightly doped drains 50 are implanted self-aligned to the gate electrode 42 and the STI structures 34. The sidewall spacers 46 are then formed. The source or drain regions 54 are then implanted self-aligned to the sidewall spacers 46 and the STI structures 34. Finally, an interlevel dielectric layer (ILD) 58 is deposited overlying the completed MOS transistor and the STI structures 34. The interlevel dielectric layer 58 is typically polished down to achieve a good planarization. Observe that typically both the STI trench filling oxide layer 34 and the interlevel dielectric layer 58 are composed of silicon dioxide. In addition, both layers are polished down in separate chemical mechanical polishing (CMP) operations.
Several prior art approaches disclose methods to form transistors and shallow trench isolations in the manufacture of an integrated circuit device. U.S. Pat. No. 5,856,225 to Lee et al discloses a method to form a MOSFET with a self-aligning channel. A temporary polysilicon gate is used in the formation of the transistor using a process that is conventional excepting delaying the threshold voltage and anti-punchthrough implants until after the MOSFET is formed. The temporary polysilicon gate is removed, the implants are performed, and then a new polysilicon layer is deposited and polished down to form the permanent gate. U.S. Pat. No. 5,786,255 to Yeh et al teaches a method to form a MOSFET with STI structures. A thick silicon nitride layer is deposited overlying the semiconductor substrate. The silicon nitride layer and the semiconductor substrate are etched to form openings for the STI. The STI is filled and planarized. Openings are etched through the silicon nitride layer where transistors are planned. Gate oxide is formed in the transistor openings. Silicide is formed in the transistor openings. The silicon nitride is removed. Sidewalls are formed on both the transistor gates and on the STI. Drains and sources are implanted. An interlevel dielectric layer is deposited and planarized. U.S. Pat. No. 5,915,183 to Gambino et al discloses a method to form raised drains and sources. A thick silicon nitride layer and the semiconductor substrate are etched to form trenches for STI. The STI are filled and planarized. Openings are etched through the silicon nitride layer for planned transistor gates. Polysilicon is deposited and planarized. The silicon nitride layer is etched to form sidewall spacers on the polysilicon gate and the STI. A second polysilicon layer is deposited to fill spaces between the STI and the polysilicon gates. The second polysilicon layer is polished down. The second polysilicon layer is recessed. The drain and source regions are formed in the second polysilicon layer. U.S. Pat. No. 5,346,584 to Nasr et al teaches a process to form STI. Trenches are etched through silicon nitride, pad oxide, and the substrate. An oxide fill layer is deposited. A polysilicon layer is deposited overlying the oxide fill layer. The polysilicon layer is patterned and oxidized to improve the oxide layer topology. The surface is then planarized.